1. Field of the Invention
The present invention relates to a semiconductor device including an island region formed in a surface area of a method of producing substrate, buried regions surrounding the island region for isolating the island region from the substrate.
2. Description of the Background Art
In FIG. 1, there is shown a conventional semiconductor device such as a CMOS, in which MOSs are electrically separated from one another by using a self-separation method in order to avoid a mutual intervention between them. In a front surface area of an n-type substrate 1, p.sup.+ -type source and drain regions 2 and 3 are formed at a certain distance away from each other, and a gate electrode 5 is formed on the substrate 1 via a gate oxide film 4 interposed therebetween between the source and drain regions 2 and 3 to obtain a p-channel MOSFET (pMOS) 8 in the right hand side portion of the substrate 1. A p-type well region 11 is also formed in the front surface area of the substrate 1. A pair of n.sup.+ -type source and drain regions 12 and 13 are formed in the surface area of the well region 11, and a gate electrode 15 is formed on the well region 11 via a gate oxide film 14 interposed therebetween between the source and drain regions 12 and 13 to obtain an n-channel MOSFET (nMOS) 18 in the left hand side portion of the substrate 1.
The pMOS 8 and the nMOS 18 each are surrounded by a field oxide film 19 formed in the surface area of the substrate 1 in order to separate the pMOS and the nMOS from each other. An insulating film 10 covers the entire surface of the obtained pMOS 8 and nMOS 18 in the substrate 1. A pair of source and drain electrodes 6 and 7 penetrate the insulating film 10 and are connected to the respective source and drain regions 2 and 3 in the pMOS 8. A pair of source and drain electrodes 16 and 17 penetrate the insulating film 10 and are connected to the respective source and drain regions 12 and 13 in the nMOS 18. In this CMOS device, the n-type substrate 1 is connected to a power source V.sub.DD (&gt;0), and the p-type well region 11 is coupled to a low voltage point, thereby electrically isolating the pMOS 8 and the nMOS 18 from each other. Thus, the pMOS 8 and the nMOS 18 can be operated independently.
However, in this CMOS device, there is provided a parastic thyristor which is composed of a series of the p.sup.+ -type source region 2, the n-type substrate 1, the p-type well region 11 and the n.sup.+ -type source region 12, and hence latch up is apt to be caused.
In FIG. 2, there is shown a conventional bipolar IC device where npn and pnp transistors are separated by using a junction separation method, i.e., a pn junction formed between the transistors. This bipolar IC device is fabricated as follows.
As shown in FIG. 2A, firstly, an n-type epitaxial layer 22 is grown on a p-type substrate 21, and p.sup.+ -type separation diffusion regions 23 are formed in the epitaxial layer 22 so as to reach the substrate 21 to obtain n-type island regions 24 between the separation diffusion regions 23. Then, as shown in FIG. 2B, a p-type base region 25 is formed in one n-type island region 24 as a collector region, and an n.sup.+ -type emitter region 26 is formed in the surface area of the p-type base region 25. An n.sup.+ -type collector contact region 27 is formed in the island region 24 to obtain an npn transistor 28. In another n-type island region 24 as a base region, p.sup.+ -type emitter and collector regions 29 and 30 and an n.sup.+ -type base contact region 31 are separately formed in the surface area to obtain a pnp transistor 32. An n.sup.+ -type buried region 33 is formed in advance between the p-type substrate 21 and the n-type island region 24. In this case, the substrate 21 is connected to a low voltage point to electrically separate the n-type island regions 24 from one another by the p.sup.+ -type separation regions 23. Hence, the npn transistor 28 and the pnp transistor 32 can be operated independently.
However, in this case, an epitaxial growing method is essential, and a process cost is expensive to invite increase of a tip producing cost.
In FIG. 3, there is shown a further conventional semiconductor device where transistors are separated from one another by using a dielectric separation method, i.e., an insulating film. As shown in FIG. 3, in a semiconductor substrate 41 such as a polycrystalline silicon, n-type island regions 43 are formed in the surface area via an insulating film 42 of SiO.sub.2 or the like for separating the island regions 43 from the substrate 41. In one island region 43 as a collector region, a p-type base region 44 is formed in the surface area, and an n.sup.+ -type emitter region 45 is formed in the surface area of the base region 44. An n.sup.+ -type collector contact region is also formed in the island region 43 to obtain an npn transistor 47. The transistors each formed in each island region 43 can be operated independently.
However, in this case, since the island regions 43 are separated by the insulating film 42, heat radiation property is bad, and destruction resisting properties against serge voltage and static electricity are low.